1. Field of the Invention
The present invention relates to the field of semiconductor memories. Specifically, embodiments of the present invention relate to a method and apparatus for handling data storage in a semiconductor memory.
2. Related Art
A conventional DRAM (dynamic random access memory) memory cell, which consists of one transistor and one capacitor, is significantly smaller than a conventional SRAM (static random access memory) cell, which typically consists of 6 transistors in a corresponding technology. However, data stored in a DRAM cell must be periodically refreshed, while the data stored in an SRAM cell has no such requirement. Each memory refresh operation of a DRAM cell utilizes memory bandwidth. If an external access and a refresh access can be initiated at the same time, the DRAM array must be able to handle both within the allowable access cycle time so as to prevent the refresh from interfering with the external access. If, for example, the cycle time of a 100 MHz DRAM array is 10 ns, each external access may take 10 ns and each refresh may take 10 ns, the external access cycle time may be no less than 20 ns. As a result, the maximum accessing frequency of the DRAM array must be less than or equal to 50 MHz. Thus, a 100 MHz DRAM memory array is required to create a device effectively operating at 50 MHz and this is not efficient.
Previous attempts to use DRAM cells in SRAM applications have been of limited success for various reasons. For example, one such DRAM device requires an external signal to control refresh operations. External accesses to this DRAM device are delayed during refresh operations, resulting in the refresh operation not being transparent. As a result, this device cannot be fully compatible with an SRAM device.
Other conventional art schemes use multi-banking to reduce the average access time of a DRAM device. These multi-banking schemes do not allow an individual memory bank to delay a refresh cycle.
In one conventional art apparatus, an SRAM compatible device is built from DRAM. This device includes a multi-bank DRAM memory and an SRAM cache that stores the most recently accessed data. (See U.S. Pat. No. 5,999,474 by Wingyu Leung et. al., “Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory”, Dec. 7, 1999.) This architecture, shown in FIGS. 1A and 1B, implements a write-back policy in which all write data is initially written to the SRAM cache prior to being written to the memory banks. The idea is to allow a refresh to occur when a cache hit occurs. When this architecture is required to sequentially write to two different banks at the same row and column address, a “ping-pong” effect takes place, creating continual cache misses, which creates a “blind hole”, not allowing a refresh cycle to take place.
Accordingly, it would be desirable to have a DRAM memory cell architecture that is fully compatible with pure SRAM devices and that creates an opportunity for a hidden refresh cycle to be performed when sequential cache misses occur at the same addressed location within different memory banks.